1. Field of the Invention
The present invention disclosed herein relates to semiconductor memories, and more particularly, to a flash memory device and a method of programming the flash memory device.
2. Description of the Related Art
Semiconductor memory devices are classified into volatile and nonvolatile types. Generally, volatile semiconductor memory devices store and read data only when power is supplied, and lose their data when no power is supplied. In comparison, nonvolatile semiconductor memory devices, such as a mask read only memory (MROM), a programmable ROM (PROM), an erasable and programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), and the like, are able to retain stored data even without power.
Data storage conditions of the nonvolatile memories are permanent or re-programmable in accordance with the technologies for manufacturing them. For example, MROM, PROM and EPROM devices generally are not flexible in independently erasing and writing data through systemic operations and are inconvenient for typical users to renew or update storage contents. EEPROM devices, though, are more convenient for electrically erasing and writing data, so these devices are increasingly used in auxiliary storage units and system programming fields requiring continuous data updates. Flash EEPROMs (referred to as “flash memories”) are particularly useful as large-capacity, auxiliary storage units because they offer higher integration density than conventional EEPROMs. In recent years, the use of flash memories as large-capacity storage units or coded memories has increased, especially in response to requirements for large storage capacity or high speed.
Flash memories are generally categorized as NOR or NAND type flash memories, in accordance with interconnections between cells and bit lines. In a NOR-flash memory, one bit line is connected to two or more cell transistors in parallel, such that data are stored in a channel hot-electron mode and erased in a Fowler-Nordheim (F-N) tunneling mode. In a NAND-flash memory, one bit line is connected to two or more cell transistors in series, such that data are stored and erased in the F-N tunneling mode. In general, the NOR-flash memories are less desirable for high-density integration due to large current consumption, but more desirable for high-frequency operations.
FIG. 1 is a sectional diagram showing a typical flash memory cell, and FIG. 2 is a diagram showing threshold-voltage distribution profiles of typical flash memory cells.
Referring to FIG. 1, the flash memory cell 10 includes a P-type substrate 11, an N-type source region 12, an N-type drain region 13, a floating gate 14, and a control gate 15. Between the source region 12 and the drain region 13 is defined a channel region 16. The floating gate 14 is formed over the channel region 16, and is isolated by an insulation film 17 from the substrate 11. The control gate 15 is formed over the floating gate 14 through another insulation film 18.
As is well known, the memory cell of the NOR-flash memory device is connected between a bit line and a source line. The memory cells coupled to a word line share the source line. The memory cell, the characteristics of which are shown in FIG. 2, is detected as an on-cell or off-cell in accordance with a word-line voltage VWL. On-cell means that the memory cell is turned on because the word-line voltage is higher than a threshold voltage of the memory cell, in which a current (i.e., the on-cell current) larger than a predetermined amount flows through the on-cell. Off-cell means that the memory cell is turned off because the word-line voltage is lower than a threshold voltage of the memory cell, in which a current smaller than a predetermined amount flows through the off-cell. Programming, erasing, and reading operations of the memory cell are as follows.
The programming operation of the memory cell 10 is accomplished by injecting hot electrons into the floating gate 14 from the channel region 16 around the drain region 13. Typically, the hot electron injection is performed under the condition that the source region 12 and the substrate 11 are grounded. A high voltage Vg (e.g., +10V) is applied to the control gate 15 and an appropriate positive voltage (e.g., 5˜6V) is applied to the drain region 13 as Vd to generate the hot electrons. Under the bias condition, negative charges are sufficiently accumulated in the floating gate 14. The negative potential of the floating gate 14 contributes to raising a threshold voltage of the memory cell 10 during the reading operation.
The reading operation of the memory cell 10 is accomplished by applying an appropriate positive voltage (e.g., 1V) to the drain region 13 as Vd, a predetermined voltage (e.g., +4.5V) to the control gate 15 as Vg, and 0V to the source region 12 as Vs. During the reading operation, the memory cell 10 has an increased threshold voltage by the programming operation, and a current is interrupted to flow toward the source region 12 from the drain region 13, which is referred to as an off-state. Threshold voltages of the programmed memory cells are usually distributed between approximately 7˜8.5V.
The erasing operation of the memory cell 10 is accomplished by inducing the Fowler-Nordheim (F-N) tunneling effect in the substrate 11 from the floating gate 14. The F-N tunneling effect is caused by applying a negative high voltage (e.g., −10V) to the control gate 15 as Vg and an appropriate positive voltage to the substrate 11 as Vb. Under the bias condition, negative charges are discharged into the substrate 11 (i.e., bulk region) from the floating gate 14, decreasing threshold voltages of the memory cells. If, during the reading operation, a predetermined voltage is applied to the control gate 15 of the memory cell 10 having the lowered threshold voltage by the erasing operation, a current path is formed from the drain region 13 toward the source region 12. The memory cell 10 in this condition is in an on-state. Threshold voltages of the erased memory cells are distributed in the range of approximately 1˜3V, as shown in FIG. 2.
The bias conditions of the erasing, programming and reading operations are summarized in FIG. 3. Erasing or programming the memory cell is performed by a command provided externally from the flash memory device (e.g., from a memory controller or host). After the programming operation, the memory cell verifies whether a threshold voltage of the programmed memory cell is practically included in a target range of threshold voltages. When the threshold voltage of the programmed memory cell is out of the target range of threshold voltages, a re-erasing or over-erasure repairing operation is carried out so that the threshold voltage of the programmed memory cell is appropriately included in the target range of threshold voltages.
FIG. 4 is a block diagram showing a schematic structure of a typical NOR-flash memory device. In particular, the configuration shown in FIG. 4 is a functional structure of a typical NOR-flash memory device.
Referring to FIG. 4, the typical NOR-flash memory device includes a memory cell array 110, a column decoder 120, a row decoder 130, and a write driver (WD) 140. The memory cell array 110 includes memory cells arranged at intersections of word lines WL0˜WLm−1 and bit lines BL0˜BLn−1. The row decoder 130 selects one of the word lines in response to a row address X_ADD and drives the selected word line with a word line voltage provided by a voltage generator (not shown). The column decoder 120 selects bit lines in response to a column address Y_ADD. The write driver 140 activates the selected bit lines, driving them to a bit line program voltage or a bit line program-inhibition voltage. For instance, when program data are input to the flash memory, the write driver 140 operates to drive the selected bit lines to the bit line program voltage (e.g., 5V). Otherwise, when program-inhibition data are input to the flash memory, the write driver 140 operates to drive the selected bit lines to the bit line program-inhibition voltage (e.g., the ground voltage).
With an increase of integration density in the flash memory devices, the number of memory cells connected to a bit line may increase, which increases bit line resistance. Along with the increase of bit line resistance, a bit line voltage (i.e., the bit line program voltage) supplied by the write driver 140 during the programming operation may be less than the required voltage, especially for memory cells farthest from the write driver 140. For example, while programming memory cells coupled to the word line WLm−1, the bit line voltage may be reduced by IR, where I is current supplied from the write driver 140 and R is bit line resistance. In the programming operation, as the voltage applied to the bit line is lowered, the memory cell is supplied with an insufficient voltage (i.e., insufficient bit line voltage). In other words, the drain may be charged with a voltage Of VBL-IR instead of the required bit line voltage VBL. This may cause the memory cell to be insufficiently programmed.